ISA - Shuang's Crypto Notes

ISA in general

When people design an ISA (Instruction Set Architecture), they are really defining the minimum set of operations a CPU must understand in order to run useful programs. At the most fundamental level, that usually boils down to four categories:

1. Arithmetic & Logic

Why? You need to actually “do work” on data.
Typical operations:
- Arithmetic: ADD, SUB (sometimes MUL and DIV are extensions)
- Bitwise logic: AND, OR, XOR, NOT
- Shifts/rotates: SLL, SRL, SRA (bit shifting)
- Comparisons: <, ==, >= (often implemented via “set less than” + branch)

2. Control Flow

Why? Programs aren’t just straight-line code; you need decisions and loops.
Typical operations:
- Conditional branches: BEQ (branch if equal), BNE (branch if not equal)
- Unconditional jumps: JAL (jump and link, used for function calls)
- Returns: JALR (indirect jump, often used for returning from functions)

This lets you implement if, for, while, and function calls/returns.

3. Memory Access (Load/Store)

Why? Data and programs live in memory; you need to fetch and update them.
Typical operations:
- LW (load word), SW (store word)
- Variants for different sizes: byte, halfword, word, doubleword
Many RISC ISAs (like RISC-V, MIPS, ARM) are load/store architectures:
- Only loads/stores access memory.
- Arithmetic and logic only operate on registers.

This simplifies CPU design and improves performance.

4. Registers & Data Model

Why? You need a fast place to hold data while computing.
An ISA defines:
- How many general-purpose registers (RISC-V has 32).
- Their width: 32-bit, 64-bit, 128-bit.
- Special registers (e.g., program counter, stack pointer, return address).

This defines the “working context” for programs.

5. (Optionally) System Instructions

Why? To interact with the outside world.
Typical minimal extras:
- ECALL (system call, to request OS services)
- EBREAK (breakpoint for debugging)
- Privileged instructions (only if you need an OS, e.g., trap handling, CSR registers).

✅ Summary

When designing a minimal ISA, you really just need:

Arithmetic & logic on integers
Control flow (branches, jumps)
Memory access (load/store)
Register set definition

Everything else — floating point, SIMD, crypto, atomics — can be extensions.

Small base integer ISA

1. What it Means

The base integer ISA in RISC-V is the minimal core set of instructions that define a working CPU.

It only supports integer arithmetic and logical operations (add, subtract, AND, OR, shifts, etc.).
It includes basic control flow (branches, jumps, function calls/returns).
It provides load/store instructions to access memory.
It defines a register set and how programs interact with it.

This “base” ISA is deliberately kept small and simple, so it can:

Run basic software, even on tiny embedded systems.
Serve as a foundation for teaching computer architecture.
Be the common ground upon which all extensions are built.

2. Example in RISC-V

RISC-V defines multiple base ISAs depending on register width:

RV32I → 32-bit base integer ISA
RV64I → 64-bit base integer ISA
RV128I → 128-bit (future-looking, not common yet)

Here the “I” stands for Integer. For example:

RV32I has 47 instructions total.
It’s enough to compile and run a C program, but without floating point or fancy operations.

3. Why It’s Important

Separating out a minimal integer-only base ISA allows:

Educational simplicity – easy to teach in classes.
Modular extensions – you only add what you need:
- M → Integer Multiplication/Division
- F/D → Floating-Point
- A → Atomic Instructions
- C → Compressed 16-bit instructions
- V → Vector Processing

So, a research project might just use RV32I, while a data-center CPU might implement RV64IMAFDV.

xlen

When we say RV32I or RV64I, the number is XLEN:

XLEN = register width (bits).
In RV32, general-purpose registers (x0–x31) are 32 bits wide.
In RV64, they are 64 bits wide.
In RV128, registers are 128 bits wide (defined in spec, but rare in real hardware).

So the distinction is not about the number of registers (it’s always 32 integer registers + 32 floating-point registers if F/D extensions are present).
It’s about the width of each register and of pointers/integers.

2. Why Register Width Defines the ISA

The register width affects:

Integer size: the “native” word size (int in C) is XLEN bits.
Pointer size: addresses are stored in general-purpose registers, so the address space is 2^XLEN.
- RV32 → 4 GB address space.
- RV64 → 16 EiB (exabytes) address space.
Instruction encoding of immediates: still 32-bit instruction words, but immediates are sign-extended to XLEN.
Arithmetic: operations are done at XLEN width. In RV64, ADD produces a 64-bit result; in RV32, it’s 32-bit.

3. Instruction Set vs Instruction Encoding

Instruction word size: RISC-V instructions are usually 32 bits wide (one word per instruction). This is independent of RV32 vs RV64 — even RV64 uses 32-bit instruction encodings.
Register width (XLEN): defines whether you’re in RV32, RV64, or RV128.
Extensions: e.g. M (multiply/divide), A (atomics), F (float), D (double float) can be added on top.

4. Practical Consequence

RV32I is good for microcontrollers (low memory, small addresses).
RV64I is good for servers/desktops (large address space, 64-bit integers).
Code written for RV32 won’t run directly on RV64 unless you recompile, because data widths and ABIs differ.

General Purpose Registers

1. What Registers Are

A register is a very small, very fast piece of storage inside the CPU.
They are directly accessible by instructions (much faster than main memory).
Think of them as the CPU’s “scratchpad” where it keeps values it’s actively working on.

2. General-Purpose vs Special-Purpose

General-purpose registers (GPRs):
- Can be used by any instruction for any kind of data (integer, address, etc.).
- Example: In RISC-V, x5 could hold an integer, or a pointer (address), depending on the program.
- Programmers and compilers decide how to use them.
Special-purpose registers (SPRs):
- Have dedicated roles in the ISA.
- Examples:
  - Program Counter (PC) – holds the address of the next instruction.
  - Stack Pointer (SP) – points to the current stack frame.
  - Status Registers / Control Registers – hold flags, privilege levels, etc.

So GPRs = flexible scratchpad, SPRs = fixed jobs.

3. General-Purpose Registers in RISC-V

RISC-V (RV32I / RV64I) defines 32 general-purpose registers, each 32-bit or 64-bit wide depending on the ISA.

They are conventionally named both as x0–x31 and with ABI (Application Binary Interface) names:

Register	ABI Name	Typical Use
x0	zero	Hardwired constant 0
x1	ra	Return address
x2	sp	Stack pointer
x3	gp	Global pointer
x4	tp	Thread pointer
x5–x7	t0–t2	Temporaries
x8	s0/fp	Saved register / frame pointer
x9	s1	Saved register
x10–x17	a0–a7	Function arguments / return values
x18–x27	s2–s11	Saved registers (callee-saved)
x28–x31	t3–t6	Temporaries

Special note: x0 is always zero — any write to it is ignored, and reading it gives 0. This is a classic RISC trick to simplify hardware and compilers.