Instruction Word
- RISC-V instructions are 32 bits wide in the base ISA (RV32I / RV64I / RV128I).
- Some extensions add compressed 16-bit instructions (C extension) or longer 48-/64-bit instructions (for special encodings), but 32-bit is the “normal” form.
A 32-bit instruction is divided into fields, depending on the format.
📜 Common Instruction Formats
RISC-V has a handful of standard formats, each designed for a class of instructions:
1. R-Type (Register type)
Used for register-register arithmetic/logical operations.
[ funct7 ][ rs2 ][ rs1 ][ funct3 ][ rd ][ opcode ] 31..25 24..20 19..15 14..12 11..7 6..0
- opcode: 7 bits → main instruction group (e.g., ALU, load/store, branch).
- rd: destination register.
- rs1, rs2: source registers.
- funct3: 3 bits → sub-operation (e.g., add vs sub vs xor).
- funct7: 7 bits → further distinguishes instructions (e.g., ADD vs SUB both use funct3=000, but funct7 differs).
👉 Example: add rd, rs1, rs2opcode = 0110011 (0x33), funct3 = 000, funct7 = 0000000.
👉 Example: sub rd, rs1, rs2
Same except funct7 = 0100000.
2. I-Type (Immediate type)
Used for instructions with an immediate operand (loads, ALU-immediate, etc.).
[ imm[11:0] ][ rs1 ][ funct3 ][ rd ][ opcode ] 31..20 19..15 14..12 11..7 6..0
- imm: 12-bit signed immediate.
- No
rs2orfunct7field here.
👉 Example: addi rd, rs1, imm.
3. S-Type (Store type)
Used for memory stores.
[ imm[11:5] ][ rs2 ][ rs1 ][ funct3 ][ imm[4:0] ][ opcode ] 31..25 24..20 19..15 14..12 11..7 6..0
- Immediate is split into high and low parts across the instruction word.
👉 Example: sw rs2, offset(rs1).
4. B-Type (Branch type)
Used for conditional branches.
[ imm[12|10:5] ][ rs2 ][ rs1 ][ funct3 ][ imm[4:1|11] ][ opcode ] 31..25 24..20 19..15 14..12 11..7 6..0
- Immediate bits are shuffled!
- Offset is sign-extended and multiplied by 2 to get branch target.
👉 Example: beq rs1, rs2, offset.
5. U-Type (Upper immediate)
Used for long immediates (lui, auipc).
[ imm[31:12] ][ rd ][ opcode ] 31..12 11..7 6..0
- Immediate is placed in upper 20 bits, lower 12 bits are zero.
6. J-Type (Jump type)
Used for jal (jump and link).
[ imm[20|10:1|11|19:12] ][ rd ][ opcode ] 31 30..21 20 19..12 11..7 6..0
- Immediate is scrambled like B-Type.
- Sign-extended, shifted left by 1.
🧩 General Rule: Opcode Determines the Format
Every RISC-V instruction has a 7-bit opcode field (bits 6..0).
This opcode tells you two things:
- Which format to use (R, I, S, B, U, J, etc.).
- Which instruction category it belongs to (arithmetic, load/store, branch, etc.).
Once you know the format, you know how to interpret the remaining bits (rd, rs1, rs2, funct3, funct7, immediate layout).
📜 Standard Opcode Map (base RV32I)
Here’s the key part of the opcode map (7 bits, binary):
| Opcode (bin) | Hex | Format | Category | Example instruction |
|---|---|---|---|---|
0110011 | 0x33 | R | Integer register-register | add, sub, xor |
0010011 | 0x13 | I | Integer register-imm | addi, xori |
0000011 | 0x03 | I | Loads | lb, lw |
0100011 | 0x23 | S | Stores | sb, sw |
1100011 | 0x63 | B | Conditional branches | beq, bne |
1101111 | 0x6F | J | Jump and link | jal |
1100111 | 0x67 | I | Jump and link register | jalr |
0110111 | 0x37 | U | Load upper immediate | lui |
0010111 | 0x17 | U | Add upper immediate to PC | auipc |
1110011 | 0x73 | I | System instructions | ecall, CSR ops |
0001011 | 0x0B | custom-0 | Reserved for custom ISA | user-defined instr. |
0101011 | 0x2B | custom-1 | Reserved for custom ISA | — |
1011011 | 0x5B | custom-2 | Reserved for custom ISA | (your case) |
1111011 | 0x7B | custom-3 | Reserved for custom ISA | — |
1. 7-bit Opcode Space
- A 7-bit field has 128 possible values (0–127 / 0x00–0x7F).
- In RISC-V, these 7 bits don’t uniquely identify an instruction by themselves.
- Instead, they act as a primary opcode:
- They tell you the instruction format (R, I, S, B, U, J).
- They narrow down the category (ALU, load, store, branch, system…).
Then, inside that category, funct3 (3 bits) and sometimes funct7 (7 bits) are used to distinguish the actual instruction.