32-bit risc-v system

RISC-V register basics

RISC-V has 32 general-purpose registers, Each one is the same width as the CPU’s word size — that is, the natural size of data the processor handles.

Byte-addressed

🧱 1️⃣ Memory is a sequence of bytes

Memory in RISC-V is organized as a long array of bytes — each byte has its own unique address.

Each byte = 8 bits.
Addresses are numbers like:

0x00000000
0x00000001
0x00000002
0x00000003
…

RISC-V registers are word-sized

For RISC-V 32-bit (RV32):

• Each register holds 32 bits = 4 bytes.

That means a word (one register’s worth of data) takes up 4 consecutive bytes in memory.

💡 3️⃣ “Byte-addressable” means…

When we say RISC-V is byte-addressable, we mean:

Each memory address points to a single byte, not a whole word.

So even though registers and data types are often 32 bits, memory is still addressed per byte.

This allows instructions like:

• LB → Load Byte
• LH → Load Halfword (2 bytes)
• LW → Load Word (4 bytes)
• SB → Store Byte
• SW → Store Word

Alignment

Because memory is byte-addressable, you can address any byte, but word accesses are typically aligned:

• Word (4 bytes) → address multiple of 4
• Halfword (2 bytes) → address multiple of 2

For example:
✅ 0x1000, 0x1004, 0x1008 → word-aligned
⚠️ 0x1001 → misaligned (can cause slower access or trap)

Why memory stays byte-addressed

Keeping memory byte-addressed (instead of word-addressed) has several advantages:

• Supports different data sizes (byte, halfword, word, doubleword)
• Easier to work with packed data or character strings
• Compatible with 32-bit RISC-V (RV32) — same address space semantics

So even in 64-bit RISC-V, addresses still count bytes, not words