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5 Types of zkEVMs
The Ethereum Foundation classifies zkEVMs into five main types based on how closely they replicate Ethereum’s existing infrastructure and execution semantics. Type 1 – Fully Ethereum-equivalent:This is the most faithful form of zkEVM, proving the entire Ethereum execution stack — including the EVM, state transitions, and gas accounting — exactly as it is today. It…
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Smaller Field in zkvm
🧮 1. Why smaller fields make zkVMs faster Your question: Why does using a smaller field lead to a more efficient zkVM? Key points you learned: ✅ In short: small fields give native-speed math and smaller data, so the zkVM runs dramatically faster. ⚖️ 2. Why “smaller” doesn’t mean “as small as possible” Your question:…
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Committing to matrices with one-hot rows
public lookup table \(T \in \mathbb{F}^{m \times m}\) \(T=\begin{bmatrix}1&0&0&…\\0&1&0&…\\0&0&1&…\\…&…&…&…\end{bmatrix}\) the table to be looked up \(M \in \mathbb{F}^{n \times m}\), the goal is to prove each row of \(M\) belongs to the rows of \(T\) for example, \(M\) is as blow (to make it more intuitive to look at) \(M=\begin{bmatrix}0&0&1&…\\1&0&0&…\\0&0&1&…\\…&…&…&…\end{bmatrix}\) form a dense representation of…
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LLVM, ZKVM, ELF
Summary of the full flow of zkvm compiling Stage What happens Output 1. Compilation Rust → LLVM IR → RISC-V machine code ELF file 2. Parsing / loading zkVM loads ELF into memory memory layout 3. Execution / simulation zkVM runs RISC-V instructions symbolically execution trace 4. Constraint generation Each step → algebraic constraint AIR…
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Twist – 1
Read only memory: checking all reads are correct is equivalent to confirming that for all cycles \( j\), the following constraint is satisfied: $$\sum\limits_{\text{register} \quad k} \mathsf{ra}(k,j) \mathsf{Val}(k)= \mathsf{rv}(j)$$ Twist: read and write: $$\sum\limits_{k \in [K]} \mathsf{ra}(k,j) \cdot \mathsf{Val}(k,j)= \mathsf{rv}(j)$$ for all the cycles \(j \in [T]\). (note the difference: \(\mathsf{Val}(k,j)\) in read write, and…
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NRK Norwegian video
use this command to download all the subtitles
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32-bit risc-v system
RISC-V register basics RISC-V has 32 general-purpose registers, Each one is the same width as the CPU’s word size — that is, the natural size of data the processor handles. Byte-addressed 🧱 1️⃣ Memory is a sequence of bytes Memory in RISC-V is organized as a long array of bytes — each byte has its…
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Two’s complement
What is two’s complement? Computers only store bits — 0s and 1s.To represent both positive and negative integers, they use two’s complement encoding. It’s called two’s complement because you take the binary complement (invert all bits) and then add 1. invert all bits -> XOR 1 4️⃣ Range of representable numbers For an n-bit two’s…
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Security level best practice
1. Security bits meaning 2. Current recommended levels (as of 2025) From NIST, ENISA, and other standards bodies: – 128-bit security is the minimum safe for general use. – 192/256-bit used when long-term or high-sensitivity protection is needed. – RSA must be very large to reach the same security: 2048-bit RSA ≈ 112-bit security (minimum…
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Neovim
I follow this video to setup vim config package I installed: NvChad Install copilot install telescope follow this video three modes: normal, insert, command line mode
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RISC-V Instructions
Resources Instruction Word A 32-bit instruction is divided into fields, depending on the format. 📜 Common Instruction Formats RISC-V has a handful of standard formats, each designed for a class of instructions: 1. R-Type (Register type) Used for register-register arithmetic/logical operations. 👉 Example: add rd, rs1, rs2opcode = 0110011 (0x33), funct3 = 000, funct7 =…
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ISA
ISA in general When people design an ISA (Instruction Set Architecture), they are really defining the minimum set of operations a CPU must understand in order to run useful programs. At the most fundamental level, that usually boils down to four categories: 1. Arithmetic & Logic 2. Control Flow This lets you implement if, for,…